Maintenance & added text

tex/misc/background_draft.bib

@@ -561,3 +561,37 @@
   year={1989},
   publisher={ACM New York, NY, USA}
 }
+
+@misc{Kjos_etal.HP-HW-CC-IO.1996,
+  copyright = {Copyright 2006 Elsevier B.V., All rights reserved.},
+  issn = {0018-1153},
+  journal = {Hewlett-Packard journal},
+  keywords = {Computer Science ; Computer Science, Hardware & Architecture ; Engineering ; Engineering, Electrical & Electronic ; Instruments & Instrumentation ; Science & Technology ; Technology},
+  language = {eng},
+  number = {1},
+  pages = {52-59},
+  publisher = {Hewlett-Packard Co},
+  abstract = {Hardware cache coherent I/O is a new feature of the PA-RISC architecture that involves the I/O hardware in ensuring cache coherence, thereby reducing CPU and memory overhead and increasing performance.},
+  author = {Kjos, Toddj and Nusbaum, Helen and Traynor, Michaelk and Voge, Brendana},
+  address = {PALO ALTO},
+  title = {Hardware cache coherent input/output},
+  volume = {47},
+  year = {1996},
+}
+
+@inproceedings{Giri_Mantovani_Carloni.NoC-CC-over-SoC.2018,
+  title={NoC-based support of heterogeneous cache-coherence models for accelerators},
+  author={Giri, Davide and Mantovani, Paolo and Carloni, Luca P},
+  booktitle={2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)},
+  pages={1--8},
+  year={2018},
+  organization={IEEE}
+}
+
+@misc{Corbet.LWN-NC-DMA.2021,
+  url={https://lwn.net/Articles/855328/},
+  journal={Noncoherent DMA mappings},
+  publisher={LWN.net},
+  author={Corbet, Jonathan},
+  year={2021}
+}